1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and particularly, to a semiconductor memory device having a redundant circuit function for electrically replacing a defective memory cell column including a defective memory cell with a spare memory cell column. The present invention has particular applicability to a dynamic random access memory device.
2. Description of the Background Art
As a semiconductor memory device is highly integrated, a defect in a memory cell is occurring increasingly. As a cause of a defect, bad conditions in the manufacturing process are mainly pointed out. For example, it is assumed that a defect occurred only in one memory cell in a semiconductor memory device having 1 megabit of memory capacity. If no measure is taken against that, that memory device has to be considered an inferior product even when there are no defects in the remaining memory cells. This means that the manufacturing efficiency, or the yield is degraded. A method of providing a redundant circuit in a memory device is known for improving the degraded yield. When a redundant circuit is provided in a memory device, for example, a defective memory cell column including a defective memory cell is electrically replaced with another spare memory cell column. For the electrical replacement, a spare memory cell column, a spare word line, a spare decoder or the like are prepared in the memory device in advance.
Some inspections before delivery are performed about a semiconductor memory device to find out the existence of a defective memory cell. When a defective memory cell is detected by the inspection, the defective memory cell column including the defective memory cell is electrically replaced with a spare memory cell column. To implement the replacement, a certain appropriate fuse is cut off among fuses previously prepared in the semiconductor memory device. Known methods for cutting a fuse off include a method utilizing a laser trimmer device cutting a fuse off by employing laser beam, and a method of melting a fuse down by providing large current to the fuse.
FIG. 1 is a block diagram of a conventional dynamic random access memory (hereinafter, referred to as "DRAM"). Referring to FIG. 1, the DRAM includes a memory cell array 4 having memory cells provided in rows and columns, a row decoder 3 for activating word lines for selecting memory cell rows, and a column decoder and a sense amplifier 5 for selecting memory cell columns and amplifying the read data signal. It is pointed out that this DRAM includes spare memory cell columns provided in an edge portion of the memory cell array 4.
FIG. 2A is a circuit diagram of the memory cell array 4 shown in FIG. 1. Referring to FIG. 2A, memory cells MC are connected to respective bit lines BL and BL. A sense amplifier 50 is connected between the bit lines BL and BL. The sense amplifier 50 is activated by turning on a NMOS transistor 11 and a PMOS transistor 12. NMOS transistors 15 and 16 are connected between the bit line pair BL, BL and an I/O line pair 23. The transistors 15 and 16 operate in response to an output signal of a column decoder 40. Switching transistors provided in the respective memory cells MC operate in response to output signals of a row decoder 3.
The column decoder 40 operates in response to column address signals CAi, CAi, CAj, CAk, CAm and CAn. When a predetermined column address signal is provided, all of the transistors 46 turn off, and all of the transistors 45 turn on. Accordingly, a node 43 is brought to ground potential through a fuse 44. As a result, NOR gates 41 or 42 generates high level signal Y1 or Y2 for a selecting memory cell column. The fuse 44 for disabling the column decoder 40 is provided in the column decoder 40. On the other hand, when the above-described predetermined column address signal is not provided, or when the fuse 44 is cut off, the node 43 becomes high level. Accordingly, the NOR gates 41 and 42 generate low level signals Y1 and Y2.
A precharging voltage generating circuit 6 is provided for precharging bit lines. The precharging voltage V.sub.BL is provided to bit line pairs through NMOS transistors 13 and 14 connected to the bit lines BL and BL. The transistors 13 and 14 operate in response to an equalizing signal EQ generated from a signal generator 70.
FIG. 2B is a circuit diagram of the spare memory cell column 4s shown in FIG. 1. Referring to FIG. 2B, the spare memory cell column 4s has a circuit configuration same as that of a common memory cell column shown in FIG. 2A. The spare column decoder 40s also has a circuit configuration almost same as that of the common column decoder 40 shown in FIG. 2A. The spare column decoder 40s, however, receives spare column signals CAjs, CAks, CAms and CAns generated by the program circuit 8 shown in FIG. 2C.
Referring to FIG. 2C, program circuit 8 includes fuses F1 through F8 for programming selection of spare memory cell columns. Each Fuse F1 through F8 is connected to receive column address signals CAj, CAj through CAn and CAn through each inverter correspondingly provided. The column address signals CAj and CAj through CAn and CAn have low level potential in a stand by state. For example, if a defective memory cell or cells exist(s) on the column specified with a column address signal (CAj, CAk, CAm, CAn)=(1, 0, 0, 0), fuses F2, F3, F5 and F7 are blown. Accordingly, when a column address signal for selecting a defective memory column is provided, high level signals CAjs, CAks, CAms and CAns are supplied as outputs. As a result, in the spare column decoder 40s shown in FIG. 2B, a spare column enable signal SCE attains a low level, so that the spare money cell column 4s is selected in response to column address signals CAi and CAi. In other words, when a programed defective memory cell column is addressed, spare memory cell column 4s is accessed instead.
FIG. 2D is a circuit diagram of the V.sub.BL generating circuit 6 shown in FIG. 2A. Referring to FIG. 2D, the V.sub.BL generating circuit 6 includes resistors R1 and R2 connected in series between the power source Vcc and ground. With voltage division of resistors R1 and R2, a precharge voltage V.sub.BL having a value of Vcc/2 is generated.
FIG. 2E is a circuit diagram of the row decoder 3 and the signal generator 70 shown in FIG. 2A and address buffer 9. Referring to FIG. 2E, the signal generator 70 generates an equalizing signal EQ and sense amplifier activating signals Sn and Sp in response to an external RAS signal. In addition, the signal generator 70 generates a row address buffer enable signal RABE and a word line driving signal .phi.x obtained by delaying an external RAS signal. Address buffer 9 receives external address signals ext. Add. Address buffer 9 generates internal address signals int.Add and int.Add in response to a signal RABE generated by signal generator 70. Row decoder 3 receives a high level word line driving signal .phi.x, and activates the specified word line WL in response to internal address signals int.Add and int.Add.
FIG. 3 is a timing chart for showing the operation of the DRAM shown in FIG. 2A. Referring to FIGS. 2A and 3, the operation of the DRAM will be described below. As a high level equalizing signal EQ is provided first, the transistors 13 and 14 are on. Thus, the bit line pair BL and BL is brought to the precharging voltage V.sub.BL. Next, after a row address strobe signal RAS falls, the signal EQ also falls. As the transistors 13 and 14 turn off in response to the signal EQ, the bit line pair BL and BL is brought into a floating state. Almost simultaneously with falling of the signal EQ, the voltage of the word line WL is raised by the row decoder 3. Accordingly, a small potential difference is produced between the bit lines BL and BL. As the signal generator 70 raises a sense amplifier activating signal Sn and makes a signal Sp fall, the sense amplifier 50 is activated. The small potential difference produced in the bit pair is amplified by the sense amplifier 50. A high level signal Y1 is provided from the column decoder 40 thereafter and the voltage amplified by the sense amplifier 50 is provided to the I/O line pair 23. The voltage provided to this I/O line pair 23 is provided outside as a data signal read from the memory cell.
Referring to FIG. 2A again, it is noted that the column decoder 40 selects two bit line pairs in response to the column address signal. That is, when the NOR gate 41 provides a high level signal Y1, upper two bit line pairs are selected. When the NOR gate 42 provides a high level signal Y2, lower two bit line pairs are selected. However, when a defect occurs in a memory cell MC connected to any of these four bit line pairs, none of the four bit line pairs is selected by the column decoder 40. That is, as the fuse 44 provided in the column decoder 40 is disconnected, the node 43 is brought to a high level. Accordingly, the respective NOR gates 41 and 42 provide low level signals Y1 and Y2, respectively. As a result, the transistors 15 through 22 turn off, and the amplified voltage of bit line pairs is not provided to the I/O line pairs 23 and 24. Consequently, the memory cell column including a defective memory cell can not be accessed. Instead of accessing these four bit line pairs, four spare bit line pairs prepared separately are accessed.
FIG. 4 is a circuit diagram for illustrating the occurrence of a defect in a memory cell MC1. As an example of a defect, the case where the word line WL1 and a bit line BL are electrically connected by a foreign material. The foreign material may be dust in the manufacturing environment of a semiconductor memory device or a residual in the etching process. Consequently, the word line WL1 and the bit line BL are connected by a resistance component 29.
When the memory cell MC1 is not selected, the row decoder 3 provides a low level signal to the word line WL1. That is to say, a transistor 32 for driving the word line WL1 turns on in response to the signal S1, and the word line WL1 is brought to a low level. The resistance component 29 is connected between the word line WL1 and the bit line BL, so that the potential of the bit line BL is gradually decreased. In other words, the potential of the bit line BL is connected to ground through the word line WL1 and the transistor 32. This causes such problems as described below.
FIG. 5 is a timing chart for illustrating abnormal reading operation caused by a memory cell defect. When a defect as shown in FIG. 4 exists in a memory cell, a read error as described below occurs. That is to say, the bit line BL is connected to ground through the resistance component 29, the word line WL1 and the transistor 32 as shown in FIG. 4, so that the precharging voltage V.sub.BL for the bit lines is gradually decreased as shown by the arrow P in FIG. 5. Especially, when a stand-by period is long, the decrease is considerable. With the decrease of the precharging voltage V.sub.BL, the potential of the equalized bit line pair BL and BL is also decreased. As a result, when a small voltage difference produced in the bit line pair BL and BL is amplified by the sense amplifier, it takes longer to raise the potential of the bit line BL. This means that it takes the sense amplifier a longer time to read data. That is, as shown in FIG. 5, after the sense amplifier is activated by the signals Sn and Sp (time t0), it takes a long time T until the voltage difference of the bit line pair BL and BL reaches a predetermined level (time t2). Therefore, when the column decoder 40 shown in FIG. 2 provides a high level signal Y1 (time t1), a sufficient voltage difference (.DELTA.V in the FIGURE) is not obtained between the bit lines BL and BL. Consequently, a read error caused by the presence of a defective memory cell has been produced in a conventional semiconductor memory device.
If the word line WL1 and the bit line BL shown in FIG. 4 are shorted, the V.sub.BL varies as shown by the chain line in FIG. 5. Accordingly, especially in this case, after activating the sense amplifier, the bit line BL takes a longer time to rise up. As a result, reading errors are caused. It is also pointed out that a state equivalent to that of short is caused when a stand by period of the DRAM is long even if short as described above is not produced.
Referring to FIG. 6, one memory cell MC includes a switching NMOS transistor Qs and a storage capacitor Cs. A cell plate voltage Vcp is supplied to one electrode of the capacitor Cs. The stored data signal is supplied to the other electrode of the capacitor Cs, and the other electrode is provided with a voltage Vce. When the stored data is "1", Vce=Vcc, and on the other hand, if the stored data is "0", Vce=0.
With a load capacitance of the bit line BL as CB, a capacitance value of the storage capacitor as CS, and a voltage of the bit line BL after activation of the word line WL as Vaft, the relationship expressed as follows holds. EQU C.sub.B .multidot.V.sub.BL +Cs (Vce-Vcp)=C.sub.B .multidot.Vaft+Cs (Vaft-Vcp) (1)
Accordingly, EQU Vaft={1/(C.sub.B +Cs)}.multidot.(C.sub.B .multidot.V.sub.BL +Cs.multidot.Vce) (2)
When the data "1" is stored in a memory cell MC, the voltage difference .DELTA.V.sub.H produced on the bit line BL upon turning-on of transistor Qs is expressed as follows. EQU .DELTA.V.sub.H =Vaft-V.sub.BL ={1/(1+C.sub.B /Cs)}.multidot.(Vce-V.sub.BL) (3)
Since the data "1" is stored, Vce.apprxeq.Vcc. Accordingly, when the V.sub.BL is at a higher level due to some trouble, sufficient .DELTA.V.sub.H is not obtained. As a result, reading errors are produced.
On the other hand, when the data "0" is stored in memory cell MC, the voltage difference .DELTA.V.sub.L produced on the bit line BL upon turning-on of the transistor Qs is expressed as follows. EQU .DELTA.V.sub.L =V.sub.BL -Vaft={1/(1+C.sub.B /Cs)}.multidot.(V.sub.BL -Vce) (4)
Since the data "0" is stored, Vce.apprxeq.0. Accordingly, when V.sub.BL is at a lower level due to such a trouble as shown in FIG. 4, sufficient .DELTA.V.sub.L is not obtained. As a result, reading errors are produced.
Referring to FIG. 7, the time length t.sub.RP of the off time period, or a stand by period of the DRAM is defined by rise and fall times of the signal RAS. It is pointed out that, as the time length t.sub.RP is longer, or the stand by period of DRAM is longer, the voltage V.sub.BL of the bit line BL is reduced due to such troubles as shown in FIG. 4. Accordingly, as shown in FIG. 8, reading errors are increased as a function of the time length t.sub.RP.